Rachinskiy Iakov, Rachinskii Dmitrii, Viventi Jonathan
Department of Biomedical Engineering, Duke University, Durham, NC, United States of America.
Department of Mathematical Sciences, University of Texas at Dallas, Richardson, TX 75080, United States of America.
J Neural Eng. 2025 Jun 6;22(3). doi: 10.1088/1741-2552/adde85.
The burgeoning demand for higher channel count neural interfaces has led to the incorporation of large connectors for connecting electrode channels to recording systems or on-site wireless electronics. However, as these devices are size-constrained for implantation, driving up pad count increases grid density, pushing metal feature sizes to their fabrication limits. Thin-film substrates offer a viable solution, as established microfabrication techniques enhance capabilities over standard electrode manufacturing. Yet, patterning thin-films (TF) still has limitations, requiring multiple layers to wire out the dense grids. This creates a trade-off: more channels require larger connectors and more routing layers, but this reduces flexibility and can make the devices too large for implantation.In this work we propose an algorithm to efficiently route dense pad grids in the worst scenario case, where traces cannot fit between adjacent pads. We show that the proposed method can route the theoretical maximum number of traces for sufficiently large grids, showing promise for application in very large channel count device designs.We demonstrate its application on a 1024 channel electrode connected to a dense, flip-chip bonded, wireless recording, application-specific integrated circuit. Comparing the algorithm to standard methods, we achieved improved efficiency in terms of routable traces, number of layers and footprint area. As channel counts increase in TF neural interfaces, escape routing will become more criticalThis algorithm addresses the challenge of mismatched pad density and metal feature size capabilities and automates the design process to ease and accelerate design iteration.
对更高通道数神经接口的迅速增长的需求，已促使采用大型连接器，用于将电极通道连接到记录系统或现场无线电子设备。然而，由于这些设备在植入时受到尺寸限制，增加焊盘数量会提高网格密度，将金属特征尺寸推向其制造极限。薄膜基板提供了一种可行的解决方案，因为既定的微制造技术比标准电极制造具有更强的能力。然而，对薄膜（TF）进行图案化仍存在局限性，需要多层来引出密集的网格。这就产生了一种权衡：更多的通道需要更大的连接器和更多的布线层，但这会降低灵活性，并且可能使设备对于植入来说太大。在这项工作中，我们提出了一种算法，用于在最坏情况下（即走线无法在相邻焊盘之间适配）有效地对密集焊盘网格进行布线。我们表明，对于足够大的网格，所提出的方法能够布出理论上的最大走线数量，这显示出在非常大通道数设备设计中的应用前景。我们展示了其在连接到密集倒装芯片键合的无线记录专用集成电路的1024通道电极上的应用。将该算法与标准方法进行比较，我们在可布线走线数量、层数和占地面积方面实现了更高的效率。随着TF神经接口中通道数的增加，迂回布线将变得更加关键。该算法解决了焊盘密度与金属特征尺寸能力不匹配的挑战，并使设计过程自动化，以简化和加速设计迭代。
