Sim Eunji, Seong Suin, Han Yeongseo, Chae Minji, Kim Taesoo, Jeong Yujeong, Choi Dahyun, Kim Hyejin, Cheong Min, Ko Changhyun, Joo Min-Kyu
Department of Applied Physics, Sookmyung Women's University, Seoul 04310, Republic of Korea.
Samsung Electronics, Yongin 17113, Republic of Korea.
ACS Appl Mater Interfaces. 2025 Jul 9;17(27):39349-39356. doi: 10.1021/acsami.5c09352. Epub 2025 Jun 25.
Two-dimensional (2D) van der Waals (vdW) materials inherently possess interlayer resistance between adjacent layers, significantly influencing their carrier distribution across the material's thickness, particularly in relation to the positioning of metal electrodes. Herein, by taking into account the Thomas-Fermi charge screening theory and a resistive network model, we systematically explore the thickness-dependent effective carrier density profile for bottom contact, top contact, and vertical double-sided contact (VDC), where the top and bottom contact electrodes are connected. VDC provides the least resistive conducting paths for carriers within 2D vdW multilayers by suppressing interlayer resistance effects, resulting in a spatial redistribution of carrier density along the thickness under varying electrostatic vertical and lateral bias conditions and consequently establishing separate bottom and top channels. The highest effective mobility, particularly for VDC, is observed at approximately 10 nm, highlighting the increasingly pivotal role of the bottom channel in the high electron accumulation regime as the thickness increases. To validate our computational results, numerous back-gated n-type WSe transistors with thicknesses ranging from 4 to 244 nm were fabricated. Superior electrical properties, including carrier mobility, conductivity, and a high on/off current ratio, were observed at thicknesses of 8 to 10 nm, in excellent agreement with our numerical calculations. Our findings offer valuable insights for advancing next-generation electronic transistors based on 2D vdW multilayers.
二维（2D）范德华（vdW）材料在相邻层之间固有地存在层间电阻，这对其载流子在材料厚度上的分布有显著影响，特别是与金属电极的位置有关。在此，通过考虑托马斯 - 费米电荷屏蔽理论和电阻网络模型，我们系统地探索了底部接触、顶部接触和垂直双面接触（VDC，即顶部和底部接触电极相连）情况下与厚度相关的有效载流子密度分布。VDC通过抑制层间电阻效应，为二维vdW多层膜内的载流子提供了电阻最小的传导路径，导致在不同的静电垂直和横向偏置条件下，载流子密度沿厚度发生空间重新分布，从而形成独立的底部和顶部通道。最高的有效迁移率，特别是对于VDC，在约10 nm处被观察到，这突出了随着厚度增加，底部通道在高电子积累区域中日益关键的作用。为了验证我们的计算结果，制备了许多厚度范围从4到244 nm的背栅n型WSe晶体管。在8到10 nm的厚度下观察到了优异的电学性能，包括载流子迁移率、电导率和高的开/关电流比，与我们的数值计算结果非常吻合。我们的发现为推进基于二维vdW多层膜的下一代电子晶体管提供了有价值的见解。
