Kim Minjae, Choi Jeongho, Kim Joongyu, Park Sung-Yun
Department of Electronic Engineering, Pusan National University, Busan 609-735, South Korea.
The Center for Wireless Integrated Micro Sening and Systems, Department of Electrical Engineering and Computer Science, University of Michigan, USA.
IEEE Sens Lett. 2025 Sep;9(9). doi: 10.1109/lsens.2025.3594060. Epub 2025 Jul 31.
This letter presents a nano-watt, low-noise, AC-coupled wideband neural recording amplifier. The nano-watt power consumption has been achieved with 1) doubling of the transconductance by using folding current transistors in a folded-cascode operational transconductance amplifier (OTA) as input transistors (folding-current-reuse (FCR) technique), that also nulls their contribution to output noise and 2) dual supplies where the high and low voltages are assigned for low and high current consuming branches, respectively. Also, the proposed FCR technique indirectly contributes to low power consumption by forming low impedance nodes, which is a difference from a conventional current-reuse OTA in a two-stage amplifier that requires Miller compensation. The amplifier with the FCR technique has been fabricated in a 180 nm standard 1P6M CMOS process. The fabricated chip has been experimentally verified both in benchtop and using a commerical silicon microelectrode. The amplifier consumes extremely low power of 266 nW from 0.4 and 0.6 V supplies, with the input referred noise of 4.9 µV in a wide bandwidth from 0.09 Hz to 7.56 kHz and exhibits 1% THD with an 2.4 mV input and an 40 dB closed-loop gain.
本文介绍了一种纳瓦级、低噪声、交流耦合宽带神经记录放大器。通过以下方式实现了纳瓦级功耗:1)在折叠共源共栅运算跨导放大器(OTA)中使用折叠电流晶体管作为输入晶体管,使跨导加倍(折叠电流复用(FCR)技术),这也消除了它们对输出噪声的贡献;2)采用双电源,其中高电压和低电压分别分配给低电流消耗支路和高电流消耗支路。此外,所提出的FCR技术通过形成低阻抗节点间接有助于降低功耗,这与需要米勒补偿的两级放大器中的传统电流复用OTA不同。采用FCR技术的放大器已在180 nm标准1P6M CMOS工艺中制造。所制造的芯片已在台式实验中以及使用商用硅微电极进行了实验验证。该放大器从0.4 V和0.6 V电源消耗极低的266 nW功率,在0.09 Hz至7.56 kHz的宽带宽内输入参考噪声为4.9 µV,在2.4 mV输入和40 dB闭环增益下表现出1%的总谐波失真。