Choi J, Bang S H, Sheu B J
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA.
IEEE Trans Neural Netw. 1993;4(3):484-95. doi: 10.1109/72.217191.
An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.
设计并制造了一种用于通信接收机应用的模拟VLSI神经网络处理器。它不需要预先估计信道特性。通过将该处理器芯片配置为四层感知器网络，实现了一个强大的信道均衡器。紧凑的突触单元由增强型宽范围吉尔伯特乘法器电路实现。输出神经元由线性电流-电压转换器和具有可控电压增益的Sigmoid函数发生器组成。网络训练通过改进的卡尔曼神经滤波算法进行，以加速符号间干扰和高斯白噪声通信信道的收敛过程。学习过程在配套的DSP板上完成，该板还保存突触权重以供芯片后续使用。该VLSI神经网络处理器芯片占用4.6 mm×6.8 mm的硅面积，采用2-μm双多晶硅CMOS技术制造。给出了系统分析和实验结果。
