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Toward a general-purpose analog VLSI neural network with on-chip learning.

作者信息

Montalvo A J, Gyurcsik R S, Paulos J J

机构信息

Ericsson Inc., Research Triangle Park, NC.

出版信息

IEEE Trans Neural Netw. 1997;8(2):413-23. doi: 10.1109/72.557695.

DOI:10.1109/72.557695
PMID:18255643
Abstract

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

摘要

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