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近期关于集成电路中铜/低介电常数介质互连的专利。

Recent patents on Cu/low-k dielectrics interconnects in integrated circuits.

作者信息

Jiang Qing, Zhu Yong F, Zhao Ming

机构信息

Key Laboratory of Automobile Materials (Jilin University), Ministry of Education and Department of Materials Science and Engineering, Jilin University, Changchun 130022, China.

出版信息

Recent Pat Nanotechnol. 2007;1(3):193-209. doi: 10.2174/187221007782360448.

Abstract

In past decades, the development of microelectronics has moved along with constant speed of scaling to maximize transistor density as driven by the need for electrical and functional performance. For further development, the propagation velocity of electromagnetic waves becomes increasingly important due to their unyielding constraints on interconnect delay. To minimize it, it was forced to the introduction of the Cu/low-k dielectric interconnects to very large scale integrated circuits (VLSI) where k denotes the dielectric constant. In addition, reliable barrier structures, which are the thinnest part among the device parts to maximize space availability for the actual Cu IWs, are required to prevent penetration of different materials. In light of the above statements, this review will focus recent patents and some studies on Cu interconnects including Cu interconnect wires, low-k dielectrics and related barrier materials as well manufacturing techniques in VLSI, which are one of the most essential concerns in microelectronic industry and decides the further development of VLSI. In addition, possible future development in this field is considered.

摘要

在过去几十年中,微电子技术的发展一直伴随着不断缩小尺寸的进程,以在电气和功能性能需求的驱动下最大化晶体管密度。为了进一步发展,由于电磁波对互连延迟有着严格的限制,其传播速度变得越来越重要。为了将其最小化,人们不得不将铜/低介电常数介质互连引入到超大规模集成电路(VLSI)中,其中k表示介电常数。此外,还需要可靠的阻挡结构,它是器件部件中最薄的部分,以最大化实际铜互连的可用空间,防止不同材料的渗透。鉴于上述情况,本综述将聚焦于近期关于铜互连的专利和一些研究,包括铜互连线、低介电常数介质及相关阻挡材料,以及超大规模集成电路中的制造技术,这些是微电子行业最核心的关注点之一,决定着超大规模集成电路的进一步发展。此外,还考虑了该领域未来可能的发展。

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