Senthilpari Chinnaiyan, Diwakar Krishnamoorthy, Singh Ajay K
Faculty of Engineering & Technology, Multimedia University, Jalan Ayer Keroh lama, 75450 Melaka, Malaysia.
Recent Pat Nanotechnol. 2009;3(1):61-72. doi: 10.2174/187221009787003311.
The paper discuss the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The divider circuits are designed by using standard CMOS 0.35 microm feature size and corresponding power supply 3.5 V. The parameters analyses are carried out by BSIM 4 analysis. We have compared the simulated results of the Shannon based divider circuit with CPL and CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response, lower latency, low EPI and high throughput.
本文讨论了使用香农定理设计1位全加器电路。该提出的全加器电路用作实现非恢复和恢复除法器电路的电路组件之一。所提出的加法器和除法器原理图使用DSCH2 CAD工具进行设计，其版图由Microwind 3 VLSI CAD工具生成。除法器电路使用标准CMOS 0.35微米特征尺寸和相应的3.5 V电源进行设计。参数分析通过BSIM 4分析进行。我们将基于香农的除法器电路的仿真结果与基于CPL和CMOS加法器单元的除法器电路进行了比较。我们进一步将结果与已发表的结果进行了比较，观察到所提出的基于加法器单元的除法器电路功耗更低、响应更快、延迟更低、EPI更低且吞吐量更高。
