DiBenedetto Sara A, Facchetti Antonio, Ratner Mark A, Marks Tobin J
Department of Chemistry and the Materials Research Center, Northwestern University, Evanston, Illinois 60208-3113, USA.
J Am Chem Soc. 2009 May 27;131(20):7158-68. doi: 10.1021/ja9013166.
Developing alternative high dielectric constant (k) materials for use as gate dielectrics is essential for continued advances in conventional inorganic CMOS and organic thin film transistors (OTFTs). Thicker films of high-k materials suppress tunneling leakage currents while providing effective capacitances comparable to those of thin films of lower-k materials. Self-assembled monolayers (SAMs) and multilayers offer attractive options for alternative OTFT gate dielectrics. One class of materials, organosilane-based self-assembled nanodielectrics (SANDs), has been shown to form robust films with excellent insulating and surface passivation properties, enhancing both organic and inorganic TFT performance and lowering device operating voltages. Since gate leakage current through the dielectric is one factor limiting continued TFT performance improvements, we investigate here the current (voltage, temperature) (I (V,T)) transport characteristics of SAND types II (pi-conjugated layer) and III (sigma-saturated + pi-conjugated layers) in Si/native SiO(2)/SAND/Au metal-insulator-metal (MIS) devices over the temperature range -60 to +100 degrees C. It is found that the location of the pi-conjugated layer with respect to the Si/SiO(2) substrate surface in combination with a saturated alkylsilane tunneling barrier is crucial in controlling the overall leakage current through the various SAND structures. For small applied voltages, hopping transport dominates at all temperatures for the pi-conjugated system (type II). However, for type III SANDs, the sigma- and pi-monolayers dominate the transport in two different transport regimes: hopping between +25 degrees C and +100 degrees C, and an apparent switch to tunneling for temperatures below 25 degrees C. The sigma-saturated alkylsilane tunneling barrier functions to reduce type III current leakage by blocking injected electrons, and by enabling bulk-dominated (Poole-Frenkel) transport vs electrode-dominated (Schottky) transport in type II SANDs. These observations provide insights for designing next-generation self-assembled gate dielectrics, since the bulk-dominated transport resulting from combining sigma- and pi-layers should enable realization of gate dielectrics with further enhanced performance.
开发用作栅极电介质的替代高介电常数（k）材料对于传统无机互补金属氧化物半导体（CMOS）和有机薄膜晶体管（OTFT）的持续发展至关重要。高k材料的较厚薄膜可抑制隧穿泄漏电流，同时提供与低k材料薄膜相当的有效电容。自组装单层（SAM）和多层膜为替代OTFT栅极电介质提供了有吸引力的选择。一类材料，基于有机硅烷的自组装纳米电介质（SAND），已被证明能形成具有优异绝缘和表面钝化性能的坚固薄膜，可提高有机和无机薄膜晶体管的性能并降低器件工作电压。由于通过电介质的栅极泄漏电流是限制TFT性能持续提升的一个因素，我们在此研究了在-60至+100摄氏度温度范围内，Si/原生SiO₂/SAND/Au金属-绝缘体-金属（MIS）器件中II型（π共轭层）和III型（σ饱和+π共轭层）SAND的电流（电压、温度）（I（V，T））传输特性。研究发现，π共轭层相对于Si/SiO₂衬底表面的位置与饱和烷基硅烷隧穿势垒相结合，对于控制通过各种SAND结构的整体泄漏电流至关重要。对于小的施加电压，在所有温度下，π共轭体系（II型）的跳跃传输占主导。然而，对于III型SAND，σ和π单层在两种不同的传输机制中占主导：在+25摄氏度至+100摄氏度之间跳跃，以及在温度低于25摄氏度时明显转变为隧穿。σ饱和烷基硅烷隧穿势垒通过阻挡注入电子以及使II型SAND中以体主导（普尔-弗伦克尔）传输而非电极主导（肖特基）传输，起到减少III型电流泄漏的作用。这些观察结果为设计下一代自组装栅极电介质提供了见解，因为σ层和π层结合产生的体主导传输应能实现性能进一步提升的栅极电介质。
