Agency for Defense Development of the Republic of Korea, Republic of Korea.
IEEE Trans Ultrason Ferroelectr Freq Control. 2010;57(2):299-304. doi: 10.1109/TUFFC.2010.1410.
In this paper we propose a method of removing from synthesizer output spurious signals due to quasi-amplitude modulation and superposition effect in a frequency-hopping synthesizer with direct digital frequency synthesizer (DDFS)-driven phase-locked loop (PLL) architecture, which has the advantages of high frequency resolution, fast transition time, and small size. There are spurious signals that depend on normalized frequency of DDFS. They can be dominant if they occur within the PLL loop bandwidth. We suggest that such signals can be eliminated by purposefully creating frequency errors in the developed synthesizer.
本文提出了一种在采用直接数字频率合成器（DDFS）驱动锁相环（PLL）架构的跳频合成器中消除由于准幅度调制和叠加效应引起的杂散信号的方法，该方法具有频率分辨率高、转换时间快和体积小等优点。DDFS 的归一化频率取决于杂散信号。如果它们出现在 PLL 环路带宽内，则可能会成为主要干扰。我们建议通过在开发的合成器中有意引入频率误差来消除这些信号。
