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基于埃尔米特插值的直接数字频率合成器优化设计

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation.

作者信息

Zhou Kunpeng, Xu Qiaoyu, Zhang Tianle

机构信息

College of Mechanical and Electrical Engineering, Henan University of Science and Technology, Luoyang 471000, China.

出版信息

Sensors (Basel). 2024 Sep 28;24(19):6285. doi: 10.3390/s24196285.

DOI:10.3390/s24196285
PMID:39409325
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC11478884/
Abstract

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of -88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

摘要

为解决资源受限环境下直接数字频率合成(DDFS)中频谱纯度欠佳的问题,本文提出一种基于三次埃尔米特插值的优化DDFS技术。首先,在现场可编程门阵列(FPGA)上实现DDFS硬件架构;随后,利用三次埃尔米特插值方法,结合正弦和余弦函数的导数关系与双端口只读存储器(ROM)结构,提取关键插值参数,以重构高保真目标波形。该方法有效缓解了DDFS数字化过程中幅度量化引起的杂散问题,同时减少了数据节点存储单元。此外,本文引入单象限ROM压缩技术,进一步减少所需存储空间。实验结果表明,与传统DDFS方法相比,本文提出的优化方案实现了1792:1的ROM资源压缩比和-88.134 dBc的14位输出无杂散动态范围(SFDR),有效提高了幅度量化精度并显著降低了杂散电平。这显著提高了幅度量化精度并降低了杂散电平。所提方案在频谱性能和资源利用效率方面均展现出显著优势,非常适合资源受限的嵌入式系统以及雷达和通信系统等高性能应用。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/6521/11478884/afa0af7b9992/sensors-24-06285-g011.jpg
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The design of a wide bandwidth time marker generator.
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A novel ROM compression architecture for DDFS utilizing the parabolic approximation of equi-section division.利用等分段抛物线逼近的直接数字频率合成器(DDFS)新型 ROM 压缩架构。
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