Trinh Van-Son, Nam Hyohyun, Song Jeong-Moon, Park Jung-Dong
Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea.
Sensors (Basel). 2022 May 10;22(10):3626. doi: 10.3390/s22103626.
A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is -92.6 dBc/Hz at 1-MHz and -106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is -85.2 dBc/Hz at 1-MHz offset.
一款用于跳频调频连续波（FMCW）雷达的W波段整数N锁相环（PLL）采用65纳米CMOS技术实现。基于对压控振荡器（VCO）及其推挽缓冲器的系统分析设计了交叉耦合压控振荡器，以实现高效率和高输出功率。为了在实现过程中不产生任何额外开销地提供跳频功能，VCO的中心频率由缓冲器的栅极电压严格控制，这有效地改变了VCO负载的电纳。制作了具有所提出架构的独立VCO，其输出功率为13.5 dBm，峰值功率效率为9.6%，调谐范围为3.5%。VCO在1兆赫偏移时的相位噪声性能为-92.6 dBc/Hz，在10兆赫偏移时为-106.1 dBc/Hz。由一个三阶环路滤波器和一个总模数为48的分频器链组成，采用交叉耦合VCO实现的PLL的锁定范围记录为78.84吉赫至84吉赫，其在1兆赫偏移时的相位噪声为-85.2 dBc/Hz。
