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基于三维模拟的杂交芯片毛细管电泳中截面面积和 Zeta 电位对分离影响的研究。

Study on the influence of cross-sectional area and zeta potential on separation for hybrid-chip-based capillary electrophoresis using 3-D simulations.

机构信息

Key Laboratory of Analytical Chemistry for Life Science, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing, PR China.

出版信息

Electrophoresis. 2010 Nov;31(22):3665-74. doi: 10.1002/elps.201000258. Epub 2010 Oct 21.

DOI:10.1002/elps.201000258
PMID:20967775
Abstract

Hybrid chips combing microchips with capillaries have displayed particular advantages in achieving UV-vis and mass spectroscopic detection. In this work, systematic 3-D numerical simulations have been carried out to explore the influence of junction interface cross-sectional area and ζ-potential distribution on sample band broadening in hybrid-chip electrophoresis separation. In this case, the ratio of cross-sectional area of chip to capillary channel (S(ratio) ) is used as the parameter of the variation in junction interface cross-sectional area. Theoretical simulations demonstrated that the decrease of the S(ratio) would increase the separation efficiency in the hybrid-chip-based CE with uniform ζ-potential distribution. ζ-potential distribution along the axial direction of the channel also affects mass transport in hybrid-chip-based CE. Therefore, the effect of ζ-potential distribution has been considered in the 3-D simulation. Theoretical simulation results reveal that ζ-potential distribution rather than the interface cross-sectional area variation (S(ratio) ) controls the sample band broadening and manipulates sample separation efficiency in the hybrid-chip-based CE with non-uniform ζ-potential distribution. Both the theoretical simulations and experimental results show that optimal hybrid-chip CE separation efficiency can be achieved at S(ratio) =1.

摘要

杂交芯片将微芯片与毛细血管结合在一起,在实现紫外可见和质谱检测方面显示出了特殊的优势。在这项工作中,我们进行了系统的三维数值模拟,以探讨在杂交芯片电泳分离中,连接界面的截面积和 ζ 电势分布对样品带展宽的影响。在这种情况下,我们使用芯片与毛细管通道的截面积比 (S(ratio) ) 作为连接界面截面积变化的参数。理论模拟表明,在具有均匀 ζ 电势分布的杂交芯片 CE 中,减小 S(ratio) 会增加分离效率。 ζ 电势沿通道轴向的分布也会影响杂交芯片 CE 中的质量传输。因此,在三维模拟中考虑了 ζ 电势分布的影响。理论模拟结果表明,在具有非均匀 ζ 电势分布的杂交芯片 CE 中,控制样品带展宽并操纵样品分离效率的是 ζ 电势分布,而不是界面截面积变化 (S(ratio) )。理论模拟和实验结果均表明,在 S(ratio) =1 时可以实现最佳的杂交芯片 CE 分离效率。

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