Research Center for Applied Sciences, Academia Sinica, Taipei, 11529, Taiwan.
Nano Lett. 2011 Sep 14;11(9):3612-6. doi: 10.1021/nl201362n. Epub 2011 Aug 15.
Direct formation of high-quality and wafer scale graphene thin layers on insulating gate dielectrics such as SiO(2) is emergent for graphene electronics using Si-wafer compatible fabrication. Here, we report that in a chemical vapor deposition process the carbon species dissociated on Cu surfaces not only result in graphene layers on top of the catalytic Cu thin films but also diffuse through Cu grain boundaries to the interface between Cu and underlying dielectrics. Optimization of the process parameters leads to a continuous and large-area graphene thin layers directly formed on top of the dielectrics. The bottom-gated transistor characteristics for the graphene films have shown quite comparable carrier mobility compared to the top-layer graphene. The proposed method allows us to achieve wafer-sized graphene on versatile insulating substrates without the need of graphene transfer.
在使用与硅晶圆兼容的制造工艺的石墨烯电子学中，直接在 SiO2 等绝缘栅介质上形成高质量和晶圆级的石墨烯薄层是非常有前景的。在这里，我们报告说，在化学气相沉积过程中，在 Cu 表面上离解的碳物种不仅导致在催化性 Cu 薄膜顶部形成石墨烯层，而且还扩散通过 Cu 晶界到达 Cu 和下面的电介质之间的界面。通过优化工艺参数，可以在电介质顶部直接形成连续且大面积的石墨烯薄层。对于石墨烯薄膜的底栅晶体管特性，与顶层石墨烯相比，载流子迁移率相当。所提出的方法允许我们在无需石墨烯转移的情况下，在各种绝缘衬底上获得晶圆级的石墨烯。
