Nanoelectronics Cluster, MIMOS Berhad, Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia.
Nanoscale Res Lett. 2011 Oct 4;6(1):543. doi: 10.1186/1556-276X-6-543.
We report on a process for fabricating self-aligned tungsten (W) nanowires with polycrystalline silicon core. Tungsten nanowires as thin as 10 nm were formed by utilizing polysilicon sidewall transfer technology followed by selective deposition of tungsten by chemical vapor deposition (CVD) using WF6 as the precursor. With selective CVD, the process is self-limiting whereby the tungsten formation is confined to the polysilicon regions; hence, the nanowires are formed without the need for lithography or for additional processing. The fabricated tungsten nanowires were observed to be perfectly aligned, showing 100% selectivity to polysilicon and can be made to be electrically isolated from one another. The electrical conductivity of the nanowires was characterized to determine the effect of its physical dimensions. The conductivity for the tungsten nanowires were found to be 40% higher when compared to doped polysilicon nanowires of similar dimensions.
我们报告了一种制造具有多晶硅芯的自对准钨（W）纳米线的方法。通过利用多晶硅侧壁转移技术，然后通过使用 WF6 作为前体的化学气相沉积（CVD）进行选择性钨沉积，形成了薄至 10nm 的钨纳米线。通过选择性 CVD，该过程是自限制的，其中钨的形成被限制在多晶硅区域内；因此，纳米线的形成不需要光刻或其他额外的处理。所制造的钨纳米线被观察到完全对齐，对多晶硅具有 100%的选择性，并且可以彼此电隔离。对纳米线的电导率进行了表征，以确定其物理尺寸的影响。与具有相似尺寸的掺杂多晶硅纳米线相比，发现钨纳米线的电导率高 40%。
