Zheng Hao, Qin Yusang, Gao Caifang, Fang Junyi, Zou Yifeng, Li Mengjiao, Zhang Jianhua
School of Microelectronics, Shanghai University, Jiading, Shanghai 201800, China.
Nanomaterials (Basel). 2025 Apr 27;15(9):666. doi: 10.3390/nano15090666.
As a critical storage technology, the material selection and structural design of flash memory devices are pivotal to their storage density and operational characteristics. Although van der Waals materials can potentially take over the scaling roadmap of silicon-based technologies, the scaling mechanisms and optimization principles at low-dimensional scales remain to be systematically unveiled. In this study, we experimentally demonstrated that the floating-gate length can significantly affect the memory window characteristics of memory devices. Experiments involving various floating-gate and tunneling-layer configurations, combined with TCAD simulations, were conducted to reveal the electrostatic coupling behaviors between floating gate and source/drain electrodes during shaping of the charge storage capabilities. Fundamental performance characteristics of the designed memory devices, including a large memory ratio (82.25%), good retention (>50,000 s, 8 states), and considerable endurance characteristics (>2000 cycles), further validate the role of floating-gate topological structures in manipulating low-dimensional memory devices, offering valuable insights to drive the development of next-generation memory technologies.
作为一种关键的存储技术，闪存器件的材料选择和结构设计对于其存储密度和操作特性至关重要。尽管范德华材料有可能取代硅基技术的缩放路线图，但低维尺度下的缩放机制和优化原则仍有待系统揭示。在本研究中，我们通过实验证明了浮栅长度会显著影响存储器件的存储窗口特性。进行了涉及各种浮栅和隧穿层配置的实验，并结合TCAD模拟，以揭示在电荷存储能力形成过程中浮栅与源极/漏极电极之间的静电耦合行为。所设计存储器件的基本性能特征，包括大存储比（82.25%）、良好的保持特性（>50,000秒，8种状态）和可观的耐久性特征（>2000次循环），进一步验证了浮栅拓扑结构在操控低维存储器件中的作用，为推动下一代存储技术的发展提供了有价值的见解。
