Wang Wei-Sheng, Tang Kea-Tiong
Annu Int Conf IEEE Eng Med Biol Soc. 2011;2011:2703-6. doi: 10.1109/IEMBS.2011.6090742.
This paper presents a successive approach register (SAR) analog-to-digital converter (ADC) with a novel hybrid digital-to-analog converter (DAC) architecture: half junction splitting (J.S.) and half binary weighted capacitor DAC. This DAC maintains low power consumption of J.S. DAC and the high signal-to-noise plus distortion ratio (SNDR) of binary weighted capacitor DAC. The power dissipation of the circuit is 1.72 μW, SNDR 59.17 dB, spurious free dynamic range (SFDR) 73.39 dB, and the FOM 23.2 fj/conversion step with 0.9 V supply voltage. The proposed circuit is fabricated in TSMC 0.18 μm 1P6M CMOS process technology.
本文提出了一种具有新型混合数模转换器(DAC)架构的逐次逼近寄存器(SAR)模数转换器(ADC):半结分裂(J.S.)和半二进制加权电容DAC。该DAC保持了J.S. DAC的低功耗以及二进制加权电容DAC的高信噪加失真比(SNDR)。电路的功耗为1.72 μW,SNDR为59.17 dB,无杂散动态范围(SFDR)为73.39 dB,在0.9 V电源电压下的优值为23.2 fj/转换步。所提出的电路采用台积电0.18μm 1P6M CMOS工艺技术制造。