Hu Yunfeng, Chen Chaoyi, Hu Lexing, Huang Qingming, Tang Bin, Hu Mengsi, Yuan Bingbing, Wu Zhaohui, Li Bin
School of Electronics and Information Engineering, University of Electronic Science and Technology of China, Zhongshan Institute, Zhongshan 528402, China.
School of Microelectronics, South China University of Technology, Guangzhou 510640, China.
Sensors (Basel). 2024 May 21;24(11):3273. doi: 10.3390/s24113273.
A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.
提出了一种用于逐次逼近寄存器型模数转换器（SAR ADC）的9 - 10位可调且节能的开关方案，该方案具有1 LSB共模电压变化。基于电容分割技术和共模转换技术，与传统方案相比，所提出的开关方案将数模转换器（DAC）的开关能量降低了96.41%。该方案的低复杂度和1 LSB共模电压偏移得益于在整个参考电压切换过程中，对应于正阵列和负阵列的电容器参考电压的同时切换，并且该方案中每个电容器的参考电压变化不超过两个电压。布局后的结果表明，在180 nm工艺、100 kS/s采样频率下，该ADC在10位模式下实现了54.96 dB的信噪比（SNDR）、61.73 dB的无杂散动态范围（SFDR）以及0.67 μW的功耗，在9位模式下实现了48.33 dB的SNDR、54.17 dB的SFDR以及0.47 μW的功耗。
