Rodriguez-Perez Alberto, Delgado-Restituto Manuel, Medeiro Fernando
IEEE Trans Biomed Circuits Syst. 2014 Jun;8(3):358-70. doi: 10.1109/TBCAS.2013.2270180. Epub 2013 Jul 26.
This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326 mm(2). The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52 μW with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv .
本文介绍了一种适用于通道内神经记录应用的基于低面积低功耗开关电容（SC）的可编程增益模数转换器（PG-ADC）。该PG-ADC采用了一种新颖的二分搜索算法实现方式，并辅以自适应偏置技术以节省功耗。它采用标准CMOS 130 nm工艺制造，仅占0.0326 mm²。PG-ADC已针对两种不同的采样模式（27 kS/s和90 kS/s）进行了优化。前者专为神经活动的原始数据转换而定制，而后者用于神经尖峰的实时特征提取。实验结果表明，在1.2 V电源电压下，无论增益设置如何，PG-ADC在两种采样模式下均获得7.56位的有效位数（8位输出）。放大增益可在0至18 dB范围内编程。PG-ADC在90 kS/s时的功耗为1.52 μW，优值为89.49 fJ/conv，而在27 kS/s时功耗为515 nW，优值为98.31 fJ/conv。
