Information and Communication System-on-Chip (SoC) Research Center, School of Electronics and Information, Kyung Hee University, Yongin 17104, Korea.
Sensors (Basel). 2022 May 9;22(9):3600. doi: 10.3390/s22093600.
This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm. At the sampling rate = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step.
本文提出了一种用于生物电位感应应用的 12 位逐次逼近寄存器 (SAR) 模数转换器 (ADC)。为了降低高分辨率 ADC 的数模转换器 (DAC) 开关能量,我们结合了合并电容器开关 (MCS) 和检测跳过 (DAS) 方法,成功地将其嵌入子范围结构中。与传统方法相比,所提出的方法节省了 96.7%的开关能量。在不增加校准电路实现负担的情况下,我们通过重复使用片上 DAC 来实现失配校准。通过在数字域中处理失配数据来补偿 DAC 失配引起的非线性。该 ADC 采用 0.18 μm CMOS 工艺实现,核心面积为 0.7 mm。在采样率为 = 9 kS/s 时,ADC 实现了 67.4 dB 的信号噪声比和失真 (SINAD)。所提出的校准技术通过提高 7.2 dB 的无杂散动态范围 (SFDR),将其提高到 73.5 dB。在增加的 = 200 kS/s 时,ADC 实现了 65.9 dB 的 SINAD 和 68.8 dB 的 SFDR,其品质因数 (FoM) 为 13.2 fJ/转换步。