Graphene Research Center, Samsung Advanced Institute of Technology, Yongin 446-712, Korea.
Science. 2012 Jun 1;336(6085):1140-3. doi: 10.1126/science.1220527. Epub 2012 May 17.
Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.
尽管对石墨烯电子学进行了多年的研究,但在具有传统器件结构的石墨烯晶体管中,始终无法获得足够的导通/截止电流比 I(on)/I(off)。我们报告了一种三端有源器件,即石墨烯可变势垒“barristor”(GB),其关键是石墨烯和氢化硅之间的原子级锐利界面。通过调节栅极电压来控制石墨烯-硅肖特基势垒,从而实现器件电流的大幅调制(导通/截止比为 10(5))。界面处不存在费米能级钉扎,这使得通过调节石墨烯的功函数可以将势垒高度调谐至 0.2 电子伏特,从而导致二极管阈值电压的大幅偏移。在各自的 150-mm 晶圆上制造 GB,并组合互补的 p 型和 n 型 GB,我们演示了反相器和半加器逻辑电路。