State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou 310027, China.
Sensors (Basel). 2013 Mar 4;13(3):3014-27. doi: 10.3390/s130303014.
This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels.
本文提出了一种基于片上可编程系统（SoPC）架构的立体视觉机器的新解决方案。SOPC 技术通过 IP 复用为访问 DDRII、SSRAM、Flash 等许多硬件设备提供了极大的便利。系统硬件在单个 FPGA 芯片中实现，其中包含 32 位 Nios II 微处理器，它是负责管理图像缓冲区和用户配置数据的可配置软 IP 核。绝对差值（SAD）算法用于密集视差图计算。算法模块的电路由基于 Matlab 的 DSP Builder 建模。通过一组配置接口，该机器可以处理许多不同大小的立体对图像。最大图像尺寸可达 512 K 像素。该机器专注于实时立体视觉应用。立体视觉机器在实时应用中具有良好的性能和效率。考虑到硬件 FPGA 时钟为 90 MHz，使用 5×5 匹配窗口和最大 64 个视差像素，每秒可获得 23 帧 640×480 视差图。
