一种具有双极性数字校准的13位噪声整形逐次逼近寄存器型模数转换器。

A 13-bit Noise Shaping SAR-ADC with Dual-Polarity Digital Calibration.

作者信息

Park Hangue, Ghovanloo Maysam

机构信息

School of Electrical and Computer Engineering, Georgia Institute of Technology.

出版信息

Analog Integr Circuits Signal Process. 2013 Jun 1;75(3):459-465. doi: 10.1007/s10470-013-0050-x.

DOI:10.1007/s10470-013-0050-x

原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC3652474/

Abstract

We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3μW power with 1.8 V supply.

摘要

我们提出了一种适用于逐次逼近寄存器型模数转换器（SAR-ADC）的新型噪声整形方法和双极性校准技术。通过添加开关电容进行噪声整形，将噪声推至更高频率。采用双极性数字校准以最小的电路开销补偿了SAR电容阵列失配。使用所提出技术的概念验证原型SAR-ADC已采用0.5μm标准CMOS技术制造。在62.5kHz采样频率下，它实现了67.7dB的信噪比，同时在1.8V电源下功耗为38.3μW。

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