IEEE Trans Biomed Circuits Syst. 2010 Dec;4(6):410-6. doi: 10.1109/TBCAS.2010.2081362.
This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm(2) .
这款 10b 50MS/s SAR 模数转换器 (ADC) 具有片上数字校准技术、比较器失调消除、电容数字模拟转换器 (CDAC) 线性度校准以及内部时钟控制功能，可补偿 PVT 变化。分置 CDAC 可减少所需单位电容器数量的指数级增长，并使输入负载电容小至 kT/C 噪声限制。采用 65nm 1P7M 互补金属氧化物半导体和 MIM 电容器制造的原型在 50MS/s、25MHz 输入频率下实现了 56.6dB 的 SNR，在包括数字校准电路在内的情况下，从 1.0V 电源消耗 820μW。在奈奎斯特条件下，性能指标为 29.7fJ/转换步。该 ADC 占用的有效面积为 0.039mm²。
