Tang Fang, Bermak Amine, Amira Abbes, Amor Benammar Mohieddine, He Debiao, Zhao Xiaojin
College of Communication Engineering, Chongqing University (CQU), China.
Hong Kong University of Science and Technology (HKUST), ECE Department, Clear Water Bay, Kowloon, Hong Kong.
ScientificWorldJournal. 2014 Jan 22;2014:861278. doi: 10.1155/2014/861278. eCollection 2014.
Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μ m CMOS technology. The chip area of the proposed ADC is 7 μ m × 500 μ m. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μ m(2) · cycles/sample.
用于CMOS图像传感器的传统两步式模数转换器（ADC）在第一级单斜率ADC中需要全分辨率噪声性能，这导致了高功耗和大芯片面积。本文提出了一种用于CMOS图像传感器应用的11位两步式单斜率/逐次逼近寄存器（SAR）ADC方案。第一级单斜率ADC生成一个3位数据和1个冗余位。使用一种提出的纠错算法将冗余位与随后的8位SAR ADC输出代码相结合。所提出的ADC的第一级单斜率电路无需全分辨率噪声性能，而是可以容忍高达3.125%的量化噪声。通过所提出的纠错机制，单斜率ADC的功耗和芯片面积显著降低。原型ADC采用0.18μm CMOS技术制造。所提出的ADC的芯片面积为7μm×500μm。测量结果表明，在所提出的ADC内核在1.4V电源下的能量效率品质因数（FOM）仅为125pJ/样本，芯片面积效率为84kμm²·周期/样本。
