This paper presents the design and testing of an electrode driving application specific integrated circuit (ASIC) intended for epidural spinal cord electrical stimulation in rats. The ASIC can deliver up to 1 mA fully programmable monophasic or biphasic stimulus current pulses, to 13 electrodes selected in any possible configuration. It also supports interleaved stimulation. Communication is achieved via only 3 wires. The current source and the control of the stimulation timing were kept off-chip to reduce the heat dissipation close to the spinal cord. The ASIC was designed in a 0.18- μm high voltage CMOS process. Its output voltage compliance can be up to 25 V. It features a small core area (<;0.36 mm(2)) and consumes a maximum of 114 μW during a full stimulation cycle. The layout of the ASIC was developed to be suitable for integration on the epidural electrode array, and two different versions were fabricated and electrically tested. Results from both versions were almost indistinguishable. The performance of the system was verified for different loads and stimulation parameters. Its suitability to drive a passive epidural 12-electrode array in saline has also been demonstrated.