Lee Seung Bae, Lee Byunghun, Gosselin Benoit, Ghovanloo Maysam
Annu Int Conf IEEE Eng Med Biol Soc. 2014;2014:3134-7. doi: 10.1109/EMBC.2014.6944287.
This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.
本文提出了一种新型的双斜率电荷采样(DSCS)模拟前端(AFE)架构,该架构通过利用电荷采样概念对神经信号进行放大,以实现模拟信号调理,如放大和滤波。所提出的DSCS-AFE以同时的方式实现放大、滤波和采样,同时功耗非常小。DSCS-AFE的输出产生一个脉宽调制(PWM)信号,该信号与输入电压幅度成正比。一个循环移位寄存器(CSR)利用PWM脉冲的时分复用(TDM)来创建一个伪数字TDM-PWM信号,该信号可以馈入无线发射器。该8通道片上系统采用0.35-μm CMOS工艺制造,占用面积为2.4×2.1 mm²,从1.8V电源获取的功耗为255μW。整个系统(包括用于恢复PWM信号的FPGA)在288 Hz至10 kHz范围内的测量输入参考噪声为6.50μV(均方根值)。对于每个通道,采样率为31.25 kHz,功耗为31.8μW。