Revathy M, Saravanan R
Department of Electronics and Communication Engineering, PSNA College of Engineering and Technology, Dindigul 624622, India.
Department of Computer Science and Engineering, RVS Educational Trust Group of Institutions, Dindigul 624005, India.
ScientificWorldJournal. 2015;2015:327357. doi: 10.1155/2015/327357. Epub 2015 Apr 29.
Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.
低密度奇偶校验（LDPC）码已应用于最新的数字视频广播、宽带无线接入（WiMax）和第四代无线标准中。在本文中，我们提出了一种用于低功耗应用的高效低密度奇偶校验码（LDPC）解码器架构。本研究还考虑了LDPC解码器架构中校验节点、变量节点单元和欧几里得正交生成器的设计与分析。欧几里得正交生成器用于降低所提出的LDPC架构的误码率，它可整合在校验节点和变量节点架构之间。所提出的解码器设计在Xilinx 9.2i平台上进行了综合，并使用Modelsim进行了仿真，其目标器件为45纳米。综合报告证明，与不同的传统架构相比，所提出的架构大大降低了功耗和硬件利用率。
