Chen Szi-Wen, Chen Yuan-Ho
Department of Electronic Engineering, Chang Gung University, Taoyuan 333, Taiwan.
Healthy Aging Research Center (HARC), Chang Gung University, Taoyuan 333, Taiwan.
Sensors (Basel). 2015 Oct 16;15(10):26396-414. doi: 10.3390/s151026396.
In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.
本文介绍了一种基于离散小波变换（DWT）的去噪方法及其在医学信号预处理降噪中的应用。这项工作聚焦于实时小波去噪过程的硬件实现。所提出的去噪电路主要由三个模块组成：一个离散小波变换模块、一个阈值处理模块和一个离散小波逆变换（IDWT）模块电路。我们还提出了一种新颖的自适应阈值处理方案，并将其纳入我们的小波去噪过程中。然后在软件的架构设计上对性能进行了评估。此外，通过将Verilog代码下载到基于现场可编程门阵列（FPGA）的平台上，还实现了去噪电路，以便在实际应用中进一步验证其降噪能力。将一组模拟的受噪声污染的心电图（ECG）信号应用于去噪电路所产生的仿真实验结果表明，该电路不仅能够理想地满足实时处理的要求，而且在降噪方面能取得令人满意的性能，同时心电图信号的尖锐特征能够得到很好的保留。所提出的去噪电路进一步使用Synopsys Design Compiler和台积电（TSMC，中国台湾新竹）40纳米标准单元库进行了综合。集成电路（IC）综合仿真结果表明，所提出的设计在200兆赫兹运行时能够实现200兆赫兹的时钟频率，功耗仅为17.4毫瓦。
