Hashim Yasir
J Nanosci Nanotechnol. 2016 Jun;16(6):5923-8. doi: 10.1166/jnn.2016.10866.
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.
本研究首次展示了纳米线N沟道金属氧化物半导体（NW-MOS）逻辑反相器的特性优化。传输特性的噪声容限和拐点电压被用作该优化中的限制因素。使用基于计算机的模型来生成NW-NMOS逻辑反相器的静态特性。在本研究中，对NW-NMOS反相器的两种电路配置进行了研究，在第一种NW-NMOS电路中，（低输入-高输出）条件下的噪声容限非常低。对于第二种NMOS电路，其噪声容限极佳，结果表明优化取决于施加到反相器的电压。以（2/1）纳米线比例增加栅极到源极电压会产生更好的噪声容限。增加施加到直流负载晶体管的电压往往会导致噪声容限降低；降低该电压将显著提高噪声容限。
