Hashim Yasir
J Nanosci Nanotechnol. 2017 Feb;17(2):1061-067. doi: 10.1166/jnn.2017.12608.
This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (V dd optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and V dd. The increase in V dd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use V dd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption.
本研究探索了基于六个硅纳米线晶体管（SiNWT）的静态随机存取存储器（SRAM）单元在不同高逻辑电平电压下的尺寸优化。本研究首次展示了具有不同逻辑电压电平（Vdd）的纳米线直径和长度对基于纳米级SiNWT的SRAM单元的优化。在该优化中，噪声容限和蝶形特性的拐点电压被用作限制因素。结果表明，优化取决于纳米线尺寸和Vdd。Vdd从1V增加到3V往往会减小优化后的纳米线尺寸，但会增加电流和功耗。使用纳米线晶体管的SRAM必须使用2V或2.5V的Vdd来生产具有更小尺寸、拐点电流和功耗的SRAM。
