Jung Hyun Soo, Ryu Ju Tae, Yoo Keon-Ho, Kim T W
J Nanosci Nanotechnol. 2016 Feb;16(2):1669-71. doi: 10.1166/jnn.2016.11950.
The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses. The electron density in the floating gate became decreased with increasing program/erase cycles. The reliability degradation occured by the increased depletion region at the bottom of the polysilicon floating gate in the continued program/erase cycle situation due to the word line stress. The degradation mechanisms for the program characteristics of 20-nm NAND flash memories were clarified by examining electron density, darin current and depletion region.
采用全三维技术计算机辅助设计模拟器对具有高k介电层的NAND闪存的电学特性进行了模拟。闪存中错误的发生率随着编程/擦除循环次数的增加而增加。为了验证字线应力效应，针对各种浮栅厚度，模拟了目标单元和非目标单元浮栅中的电子密度、非目标单元沟道中的漏极电流以及非目标单元的耗尽区随编程/擦除循环的变化情况。浮栅中的电子密度随着编程/擦除循环次数的增加而降低。由于字线应力，在持续的编程/擦除循环情况下，多晶硅浮栅底部的耗尽区增加导致了可靠性下降。通过研究电子密度、漏极电流和耗尽区，阐明了20纳米NAND闪存编程特性的退化机制。
