You Kaikai, Jin Lei, Jia Jianquan, Huo Zongliang
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Micromachines (Basel). 2023 Oct 9;14(10):1916. doi: 10.3390/mi14101916.
To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.
为了满足对更多字线（WL）层不断增长的需求，双层甚至三层架构已出现在3D NAND闪存中。然而，在两层的接合区域出现的新可靠性问题成为了开发多层技术的严峻挑战。这项工作报告了在多次循环下，联合区域（联合虚拟字线）的虚拟字线擦除干扰引入的异常可靠性问题。更具体地说，经过几次擦除循环应力后，由于操作应力导致联合虚拟字线的阈值电压（Vt）增加，最终将对相邻的数据字线造成额外干扰。在本文中，基于我们的TCAD模拟结果，我们提出擦除过程中的这种干扰源于通过FN隧穿反向注入的电子。此外，我们还提出了一种优化的擦除方案，以减少反向电子注入并抑制擦除循环期间联合虚拟字线的异常干扰。
