Department of Physics, Case Western Reserve University, Cleveland, OH 44106, USA.
Nanoscale. 2016 Dec 7;8(45):19050-19057. doi: 10.1039/c6nr07098a. Epub 2016 Nov 7.
Gate tunable p-type multilayer tin mono-sulfide (SnS) field-effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performance. The devices showed anisotropic inplane conductance and room temperature field effect mobilities ∼5-10 cm V s. However, the devices showed an ON-OFF ratio ∼10 at room temperature due to appreciable OFF state conductance. The weak gate tuning behavior and finite OFF state conductance in the depletion regime of SnS devices are explained by the finite carrier screening length effect which causes the existence of a conductive surface layer from defect induced holes in SnS. Through etching and n-type surface doping by CsCO to reduce/compensate the not-gatable holes near the SnS flake's top surface, the devices exhibited an order of magnitude improvement in the ON-OFF ratio, and a hole Hall mobility of ∼100 cm V s at room temperature is observed. This work suggests that in order to obtain effective switching and low OFF state power consumption, two-dimensional (2D) semiconductor based depletion mode FETs should limit their thickness to within the Debye screening length of the carriers in the semiconductor.
我们制备并研究了栅可调 p 型多层锡单硫化物 (SnS) 场效应晶体管 (FET) 器件，其 SnS 厚度在 50nm 至 100nm 之间，以了解其性能。器件表现出各向同性的面内电导和室温下约为 5-10cm V s 的场效应迁移率。然而，由于可观的关态电导，器件在室温下表现出约 10 的导通-关断比。SnS 器件耗尽区中栅极调谐行为较弱和有限的关态电导可归因于有限的载流子屏蔽长度效应，该效应导致在 SnS 中由缺陷诱导的空穴存在导电表面层。通过刻蚀和 CsCO 进行 n 型表面掺杂以减少/补偿 SnS 薄片顶部表面附近的不可栅控空穴，器件的导通-关断比提高了一个数量级，在室温下观察到空穴霍尔迁移率约为 100cm V s。这项工作表明，为了获得有效的开关和低关态功率消耗，基于二维 (2D) 半导体的耗尽模式 FET 应将其厚度限制在半导体中载流子的德拜屏蔽长度内。
