Toward the Understanding of Selective Si Nano-Oxidation by Atomic Scale Simulations.

The continuous miniaturization of nanodevices, such as transistors, solar cells, and optical fibers, requires the controlled synthesis of (ultra)thin gate oxides (<10 nm), including Si gate-oxide (SiO) with high quality at the atomic scale. Traditional thermal growth of SiO on planar Si surfaces, however, does not allow one to obtain such ultrathin oxide due to either the high oxygen diffusivity at high temperature or the very low sticking ability of incident oxygen at low temperature. Two recent techniques, both operative at low (room) temperature, have been put forward to overcome these obstacles: (i) hyperthermal oxidation of planar Si surfaces and (ii) thermal or plasma-assisted oxidation of nonplanar Si surfaces, including Si nanowires (SiNWs). These nano-oxidation processes are, however, often difficult to study experimentally, due to the key intermediate processes taking place on the nanosecond time scale. In this Account, these Si nano-oxidation techniques are discussed from a computational point of view and compared to both hyperthermal and thermal oxidation experiments, as well as to well-known models of thermal oxidation, including the Deal-Grove, Cabrera-Mott, and Kao models and several alternative mechanisms. In our studies, we use reactive molecular dynamics (MD) and hybrid MD/Monte Carlo simulation techniques, applying the Reax force field. The incident energy of oxygen species is chosen in the range of 1-5 eV in hyperthermal oxidation of planar Si surfaces in order to prevent energy-induced damage. It turns out that hyperthermal growth allows for two growth modes, where the ultrathin oxide thickness depends on either (1) only the kinetic energy of the incident oxygen species at a growth temperature below T = 600 K, or (2) both the incident energy and the growth temperature at a growth temperature above T. These modes are specific to such ultrathin oxides, and are not observed in traditional thermal oxidation, nor theoretically considered by already existing models. In the case of thermal or plasma-assisted oxidation of small Si nanowires, on the other hand, the thickness of the ultrathin oxide is a function of the growth temperature and the nanowire diameter. Below T, which varies with the nanowire diameter, partially oxidized SiNW are formed, whereas complete oxidation to a SiO nanowire occurs only above T. In both nano-oxidation processes at lower temperature (T < T), final sandwich c-Si|SiO|a-SiO structures are obtained due to a competition between overcoming the energy barrier to penetrate into Si subsurface layers and the compressive stress (∼2-3 GPa) at the Si crystal/oxide interface. The overall atomic-simulation results strongly indicate that the thickness of the intermediate SiO (x < 2) region is very limited (∼0.5 nm) and constant irrespective of oxidation parameters. Thus, control over the ultrathin SiO thickness with good quality is indeed possible by accurately tuning the oxidant energy, oxidation temperature and surface curvature. In general, we discuss and put in perspective these two oxidation mechanisms for obtaining controllable ultrathin gate-oxide films, offering a new route toward the fabrication of nanodevices via selective nano-oxidation.