Chen Chun-Chi, Chu Che-Hsun
Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, No. 2, Jhuoyue Rd., Nanzih District, Kaohsiung City 811, Taiwan.
Rev Sci Instrum. 2017 Feb;88(2):024704. doi: 10.1063/1.4975099.
This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.
本文提出了一种基于脉冲扩展的新型全数字CMOS数模转换器（DTC）。脉冲扩展通过全数字脉冲混合方案实现，该方案可有效提高定时分辨率并使DTC结构简洁。该DTC无需游标原理或昂贵的数模转换器，它包括用于生成脉冲的脉冲发生器、用于对定时生成进行编程的脉冲扩展电路（PEC）以及用于消除脉冲时间宽度的时间减法器。PEC仅由一个由所提出的脉冲扩展单元组成的延迟链和一个多路复用器构成。为提高精度，提出了一种脉冲中和技术以消除不良的脉冲变化。一个4位转换器采用0.35μm台积电CMOS工艺制造，面积小，约为0.045平方毫米。测试了六颗芯片，所有芯片均表现出更高的分辨率（约16皮秒）和低积分非线性（小于±0.4最低有效位）。当采样率为1M样本/秒且电源电压为3.3V时，功耗为0.2毫瓦。所提出的DTC不仅具有良好的成本和功耗，而且无需先进的CMOS工艺就能实现可接受的分辨率。本研究首次在数模转换中使用脉冲扩展。
