Cheng Zeng, Deen M Jamal, Peng Hao
IEEE Trans Biomed Circuits Syst. 2016 Apr;10(2):445-54. doi: 10.1109/TBCAS.2015.2434957. Epub 2015 Jul 7.
In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 mm(2). Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date.
本文提出了一种高分辨率、高精度和超低功耗的时间数字转换器（TDC）。所提出的TDC基于可门控的游标环形振荡器架构。通过以游标配置排列的两个环形振荡器实现了高分辨率。该TDC采用单转换结束检测电路，并在转换完成时关闭环形振荡器以降低功耗。原型芯片采用标准的130nm数字CMOS工艺制造，其面积仅为0.03mm²。使用1.2V电源时，该TDC的分辨率为7.3ps，单次精度为1.0LSB，平均功耗为1.2mW。借助INL查找表校准，获得了1.2LSB的均方根积分非线性（INL）。与先前报道的基于环形振荡器的TDC相比，所提出的设计实现了迄今为止最低的功耗。
