Shan Dan, Qian Mingqing, Ji Yang, Jiang Xiaofan, Xu Jun, Chen Kunji
National Laboratory of Solid State Microstructures and School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China.
School of Electronic and Information Engineering, Yangzhou Polytechnic Institute, Yangzhou 225127, China.
Nanomaterials (Basel). 2016 Dec 3;6(12):233. doi: 10.3390/nano6120233.
Nano-crystalline Si films with high conductivities are highly desired in order to develop the new generation of nano-devices. Here, we first demonstrate that the grain boundaries played an important role in the carrier transport process in un-doped nano-crystalline Si films as revealed by the temperature-dependent Hall measurements. The potential barrier height can be well estimated from the experimental results, which is in good agreement with the proposed model. Then, by introducing P and B doping, it is found that the scattering of grain boundaries can be significantly suppressed and the Hall mobility is monotonously decreased with the temperature both in P- and B-doped nano-crystalline Si films, which can be attributed to the trapping of P and B dopants in the grain boundary regions to reduce the barriers. Consequently, a room temperature conductivity as high as 1.58 × 10³ S/cm and 4 × 10² S/cm is achieved for the P-doped and B-doped samples, respectively.
为了开发新一代纳米器件,人们迫切需要具有高电导率的纳米晶硅薄膜。在此,我们首次证明,通过与温度相关的霍尔测量表明,晶界在未掺杂的纳米晶硅薄膜的载流子传输过程中起着重要作用。根据实验结果可以很好地估算出势垒高度,这与所提出的模型高度吻合。然后,通过引入P和B掺杂,发现晶界散射可得到显著抑制,并且在P掺杂和B掺杂的纳米晶硅薄膜中,霍尔迁移率均随温度单调下降,这可归因于P和B掺杂剂在晶界区域的俘获从而降低了势垒。因此,P掺杂和B掺杂样品分别实现了高达1.58×10³ S/cm和4×10² S/cm的室温电导率。