Vornicu Ion, Carmona-Galán Ricardo, Rodríguez-Vázquez Ángel
Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Américo Vespucio s/n, Parque Científico y Tecnológico de La Cartuja, Seville 41092, Spain.
Sensors (Basel). 2017 May 9;17(5):1072. doi: 10.3390/s17051072.
The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters' variation.
基于具有像素内时间数字转换器（TDC）的单光子雪崩二极管（SPAD）阵列的直接飞行时间互补金属氧化物半导体（CMOS）图像传感器（dToF-CIS）的设计必须考虑影响其整体性能的系统级因素。本文详细分析了工艺参数、电源电压和温度（PVT）变化对TDC阵列时间间隔的影响。此外，还介绍了一种全局补偿环路的设计与特性。它基于片上集成的锁相环（PLL）。PLL的主要组成部分是一个压控环形振荡器（VCRO），与用于像素内TDC的振荡器相同。驱动主VCRO的参考电压被分配到从VCRO的电压控制输入，使得它们的多相输出对PVT变化保持不变。这些输出用作TDC的时间内插器。因此，补偿方案可防止TDC的时间间隔由于上述因素随时间漂移。此外，相同的方案用于对旨在进行三维测距或深度图成像的直接飞行时间（ToF）成像器的不同时间分辨率进行编程。还提供了验证该分析的实验结果。补偿环路被证明非常有效。当温度范围从0°C到100°C时，TDC时间间隔的扩展从20%降低到2.4%；当电源电压在标称值的±10%范围内变化时，从27%降低到0.27%；由于工艺参数变化，在30个样本芯片上，标准偏差从5.2 ps降低到2 ps。
