Parsakordasiabi Mojtaba, Vornicu Ion, Rodríguez-Vázquez Ángel, Carmona-Galán Ricardo
Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Américo Vespucio s/n, Parque Científico y Tecnológico de La Cartuja, 41092 Seville, Spain.
Sensors (Basel). 2021 Jan 5;21(1):308. doi: 10.3390/s21010308.
In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [-0.953, 1.185] LSB, and an integral non-linearity (INL) within [-2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.
在本文中，我们提出了一种基于现场可编程门阵列（FPGA）的时间数字转换器（TDC）架构，以在低资源使用情况下实现高性能。该TDC可用于多通道直接飞行时间（ToF）应用。所提出的架构由同步输入阶段、调谐抽头延迟线（TDL）、一和零计数器的组合编码器以及在线校准阶段组成。该TDC在Artix-7 FPGA中的实验结果显示，差分非线性（DNL）在[-0.953, 1.185] LSB范围内，积分非线性（INL）在[-2.750, 1.238] LSB范围内。测量得到的LSB大小和精度分别为22.2 ps和26.04 ps。此外，所提出的架构需要的FPGA资源较少。
