Kim Sangwan, Choi Woo Young
Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea.
Department of Electronic Engineering, Sogang University, Seoul 04107, Korea.
J Nanosci Nanotechnol. 2018 Sep 1;18(9):5953-5958. doi: 10.1166/jnn.2018.15578.
In this manuscript, the compact potential model for double-gate (DG) Si1-xGex/Si heterojunction tunnel field-effect transistors (TFETs) is proposed by adopting several strategies to the previous model. Compared with the control model, the enhanced model can describe the effects of additional parameters such as electron permittivity and Si1-xGex affinity, doping dependent bandgap narrowing, temperature, built-in potential change due to degenerately doping condition and energy band off-sets. The model accuracy is examined by benchmarking against to the technology computeraided design (TCAD) device simulations in terms of electrostatic potential profiles, band diagrams and minimum tunneling barrier width (Wt, min). As a result, the enhanced model accurately describes Wt, min in various gate voltages with different Ge mole fractions and gate oxide thicknesses. The DG heterojunction TFETs are regarded as one of the most promising successors to metal-oxide-semiconductor FETs (MOSFETs) as ultra-low-power logic devices, due to their high compatibility with complementary MOS (CMOS)-based integrated circuits (ICs) in terms of structures, materials and fabrication processes. The proposed enhanced model is expected to contribute for examining the TFETs circuit operation as well as understanding device physics, in depth, to extend Moore's Law.
在本手稿中，通过对先前模型采用多种策略，提出了用于双栅（DG）Si1-xGex/Si异质结隧道场效应晶体管（TFET）的紧凑型势模型。与控制模型相比，增强模型可以描述诸如电子介电常数和Si1-xGex亲和性、掺杂相关的带隙变窄、温度、简并掺杂条件引起的内建电势变化以及能带偏移等附加参数的影响。通过与技术计算机辅助设计（TCAD）器件模拟在静电势分布、能带图和最小隧穿势垒宽度（Wt, min）方面进行基准测试来检验模型精度。结果，增强模型准确地描述了在具有不同Ge摩尔分数和栅氧化层厚度的各种栅极电压下的Wt, min。由于双栅异质结TFET在结构、材料和制造工艺方面与基于互补MOS（CMOS）的集成电路（IC）具有高度兼容性，因此它们被视为作为超低功耗逻辑器件的金属氧化物半导体场效应晶体管（MOSFET）最有前途的继任者之一。预计所提出的增强模型将有助于深入研究TFET的电路操作以及理解器件物理，以扩展摩尔定律。
