Lee Changhee, Rathi Servin, Khan Muhammad Atif, Lim Dongsuk, Kim Yunseob, Yun Sun Jin, Youn Doo-Hyeb, Watanabe Kenji, Taniguchi Takashi, Kim Gil-Ho
School of Electronic and Electrical Engineering and Sungkyunkwan Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon 16419, Republic of Korea.
Nanotechnology. 2018 Aug 17;29(33):335202. doi: 10.1088/1361-6528/aac6b0. Epub 2018 May 22.
Molybdenum disulfide (MoS) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS flake are fabricated on hBN and SiO substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS-SiO and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS layer with a single hBN on both the devices. The device to device variations induced by different MoS layer is also eliminated by employing a single MoS layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 10 cm on hBN substrate as compared to 1.1 × 10 cm on SiO substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS FETs.
基于二硫化钼(MoS)的场效应晶体管(FET)在电子和光电子应用中备受关注,但往往存在较大的滞后现象和阈值电压不稳定性。在本研究中,通过使用先进的转移技术,在六方氮化硼(hBN)和SiO衬底上制备了基于单个、均匀且原子级薄的MoS薄片的hBN封装FET。这使得能够更好且精确地比较MoS-SiO和hBN界面处半导体-电介质界面的电荷陷阱。通过在两个器件上都用单个hBN封装有源MoS层,可将环境和实体对滞后现象的影响降至最低。通过使用单个MoS层来制造两个器件,还消除了由不同MoS层引起的器件间变化。在消除这些导致器件特性变化的额外因素后,测量发现hBN衬底上的俘获电荷密度降至1.9×10 cm,而SiO衬底上为1.1×10 cm。此外,在hBN衬底上观察到滞后现象减少且阈值电压稳定,还研究了它们对栅极扫描速率、扫描范围和栅极应力的依赖性。SiO和hBN衬底上封装器件之间的这种精确比较进一步证明了hBN衬底和封装对于改善MoS FET性能并使其稳定的必要性。