Qiao Zhitong, Han Yan, Han Xiaoxia, Xu Han, Li Will X Y, Song Dong, Berger Theodore W, Cheung Ray C C
Institute of Microelectronics and Nanoelectronics, Zhejiang University, Hangzhou 310027, China
School of Medicine, Zhejiang University, Hangzhou 310058, China
Neural Comput. 2018 Sep;30(9):2472-2499. doi: 10.1162/neco_a_01107. Epub 2018 Jun 27.
A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)-generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.
海马体假体是一种需要植入生物大脑以解决认知功能障碍的超大规模集成（VLSI）生物芯片。在这封信中，我们提出了一种用于海马体假体的新型低复杂度、小面积且低功耗的可编程海马体神经网络专用集成电路（ASIC）。它基于海马体的非线性动力学模型：即多输入多输出（MIMO）广义拉盖尔 - 沃尔泰拉模型（GLVM）。它能够实现海马体神经活动的实时预测。文中提出了新的硬件架构、存储空间配置方案、低功耗卷积以及高斯随机数生成器模块。该ASIC采用40纳米工艺制造，核心面积为0.122平方毫米，测试功耗为84.4微瓦。与基于传统架构的设计相比，实验结果表明该芯片的核心面积减少了84.94%，核心功耗降低了24.30%。
