低关断损耗4H-SiC沟槽绝缘栅双极型晶体管的仿真研究

Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss.

作者信息

Mao Hong-Kai, Wang Ying, Wu Xue, Su Fang-Wen

机构信息

The Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi University, Hangzhou 310018, China.

National Key Laboratory of Analog Integrated Circuits, Chongqing 400060, China.

出版信息

Micromachines (Basel). 2019 Nov 26;10(12):815. doi: 10.3390/mi10120815.

DOI:10.3390/mi10120815

PMID:31779077

原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC6952884/

Abstract

In this work, an insulated gate bipolar transistor (IGBT) is proposed that introduces a portion of the p-polySi/p-SiC heterojunction on the collector side to reduce the tail current during device turn-offs. By adjusting the doping concentration on both sides of the heterojunction, the turn-off loss is further reduced without sacrificing other characteristics of the device. The electrical characteristics of the device were simulated through the Silvaco ATLAS 2D simulation tool and compared with the traditional structure to verify the design idea. The simulation results show that, compared with the traditional structure, the turn-off loss of the proposed structure was reduced by 58.4%, the breakdown voltage increased by 13.3%, and the forward characteristics sacrificed 8.3%.

摘要

在这项工作中，提出了一种绝缘栅双极晶体管（IGBT），该晶体管在集电极侧引入了一部分p型多晶硅/p型碳化硅异质结，以减少器件关断期间的拖尾电流。通过调整异质结两侧的掺杂浓度，在不牺牲器件其他特性的情况下进一步降低了关断损耗。通过Silvaco ATLAS 2D模拟工具对该器件的电学特性进行了模拟，并与传统结构进行了比较，以验证设计理念。模拟结果表明，与传统结构相比，所提出结构的关断损耗降低了58.4%，击穿电压提高了13.3%，正向特性牺牲了8.3%。