Hirtzlin Tifenn, Bocquet Marc, Penkovsky Bogdan, Klein Jacques-Olivier, Nowak Etienne, Vianello Elisa, Portal Jean-Michel, Querlioz Damien
C2N, Univ Paris-Sud, Université Paris-Saclay, CNRS, Palaiseau, France.
Aix Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, France.
Front Neurosci. 2020 Jan 9;13:1383. doi: 10.3389/fnins.2019.01383. eCollection 2019.
The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions and reliance on low-precision computation. The emergence of resistive memory technologies indeed provides an opportunity to tightly co-integrate logic and memory in hardware. In parallel, the recently proposed concept of a Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy for implementing low-energy Binarized Neural Networks that employs brain-inspired concepts while retaining the energy benefits of digital electronics. We design, fabricate, and test a memory array, including periphery and sensing circuits, that is optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130-nm CMOS process, in a two-transistor, two-resistor cell, which allows the exclusive NOR operations of the neural network to be performed directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows a reduction in the number of bit errors on the synaptic weights without the use of formal error-correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet, and an ECG task) that the system has inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches and that it can use memory devices in regimes where they exhibit particularly low programming energy and high endurance. We conclude the work by discussing how it associates biologically plausible ideas with more traditional digital electronics concepts.
大脑以极低的能量消耗执行智能任务。这项工作的灵感来自大脑用于实现这种能量效率的两种策略:计算和存储功能不分离以及依赖低精度计算。电阻式存储技术的出现确实为在硬件中紧密集成逻辑和存储提供了机会。与此同时,最近提出的二值化神经网络概念,即用异或非(XNOR)逻辑门取代乘法运算,提供了一种使用非常低精度计算来实现人工智能的方法。因此,在这项工作中,我们提出了一种实现低能耗二值化神经网络的策略,该策略采用受大脑启发的概念,同时保留数字电子学的能量优势。我们设计、制造并测试了一个内存阵列,包括外围和传感电路,该阵列针对这种内存计算方案进行了优化。我们的电路采用集成在130纳米CMOS工艺后端的氧化铪电阻式存储器,采用双晶体管、双电阻单元,这使得神经网络的异或非运算能够直接在传感放大器内执行。基于广泛的电学测量,我们表明我们的设计在不使用形式纠错码的情况下减少了突触权重上的误码数量。我们使用这个内存阵列设计了一个完整的系统。在标准机器学习任务(MNIST、CIFAR - 10、ImageNet和一个心电图任务)中,我们表明该系统对位错误具有内在的弹性。我们证明,与更标准的方法相比,其能耗具有吸引力,并且它可以在内存设备表现出特别低的编程能量和高耐久性的状态下使用这些设备。我们通过讨论这项工作如何将生物学上合理的想法与更传统的数字电子学概念联系起来来结束这项工作。