Xu Changqing, Zhang Wenrui, Liu Yu, Li Peng
School of Microelectronics, Xidian University, Xi'an, China.
Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA, United States.
Front Neurosci. 2020 Feb 14;14:104. doi: 10.3389/fnins.2020.00104. eCollection 2020.
Spiking neural networks (SNNs) are the third generation of neural networks and can explore both rate and temporal coding for energy-efficient event-driven computation. However, the decision accuracy of existing SNN designs is contingent upon processing a large number of spikes over a long period. Nevertheless, the switching power of SNN hardware accelerators is proportional to the number of spikes processed while the length of spike trains limits throughput and static power efficiency. This paper presents the first study on developing temporal compression to significantly boost throughput and reduce energy dissipation of digital hardware SNN accelerators while being applicable to multiple spike codes. The proposed compression architectures consist of low-cost input spike compression units, novel input-and-output-weighted spiking neurons, and reconfigurable time constant scaling to support large and flexible time compression ratios. Our compression architectures can be transparently applied to any given pre-designed SNNs employing either rate or temporal codes while incurring minimal modification of the neural models, learning algorithms, and hardware design. Using spiking speech and image recognition datasets, we demonstrate the feasibility of supporting large time compression ratios of up to 16×, delivering up to 15.93×, 13.88×, and 86.21× improvements in throughput, energy dissipation, the tradeoffs between hardware area, runtime, energy, and classification accuracy, respectively based on different spike codes on a Xilinx Zynq-7000 FPGA. These results are achieved while incurring little extra hardware overhead.
脉冲神经网络（SNN）是第三代神经网络，能够探索速率编码和时间编码，以实现高能效的事件驱动计算。然而，现有SNN设计的决策准确性取决于在较长时间内处理大量脉冲。尽管如此，SNN硬件加速器的开关功率与处理的脉冲数量成正比，而脉冲序列的长度限制了吞吐量和静态功率效率。本文首次开展了关于开发时间压缩技术的研究，以显著提高数字硬件SNN加速器的吞吐量并降低能耗，同时适用于多种脉冲编码。所提出的压缩架构包括低成本的输入脉冲压缩单元、新颖的输入和输出加权脉冲神经元，以及可重构的时间常数缩放，以支持大且灵活的时间压缩比。我们的压缩架构可以透明地应用于任何采用速率编码或时间编码的预先设计好的SNN，同时对神经模型、学习算法和硬件设计的修改最小。使用脉冲语音和图像识别数据集，我们证明了支持高达16倍的大时间压缩比的可行性，基于Xilinx Zynq-7000 FPGA上的不同脉冲编码，分别在吞吐量、能耗、硬件面积、运行时间、能量和分类准确性之间的权衡方面实现了高达15.93倍、13.88倍和86.21倍的提升。这些结果是在几乎不产生额外硬件开销的情况下实现的。
