Dodson J P, Holman Nathan, Thorgrimsson Brandur, Neyens Samuel F, MacQuarrie E R, McJunkin Thomas, Foote Ryan H, Edge L F, Coppersmith S N, Eriksson M A
Department of Physics, University of Wisconsin-Madison, Madison, WI 53706, United States of America.
HRL Laboratories, LLC, 3011 Malibu Canyon Road, Malibu, CA 90265, United States of America.
Nanotechnology. 2020 Dec 11;31(50):505001. doi: 10.1088/1361-6528/abb559.
We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.
我们展示了一种用于在Si/SiGe异质结构上制造重叠铝栅量子点器件的改进工艺，该工艺包括低温栅间氧化、栅氧化层的热退火、片上静电放电（ESD）保护以及出于热预算考虑的优化互连工艺。此工艺减少了栅极间泄漏、ESD造成的损伤、铝的去湿以及器件互连中不期望合金的形成。此外，随着器件几何形状的变化，横截面扫描透射电子显微镜（STEM）图像阐明了有源区中的栅电极形态。我们表明，重叠的铝栅层均匀地符合其下方的拓扑结构，与栅极几何形状无关，并确定了栅极几何形状中图案转移变得不理想从而导致器件故障的关键尺寸。
