Yen Te Jui, Chin Albert, Gritsenko Vladimir
Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
Rzhanov Institute of Semiconductor Physics, Siberian Branch, Russian Academy of Sciences, 630090 Novosibirsk, Russia.
Nanomaterials (Basel). 2020 Oct 28;10(11):2145. doi: 10.3390/nano10112145.
Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO TFTs, with a high field-effect mobility () of 136 cm/Vs, a large on-current/off-current (I/I) of 1.5 × 10, and steep subthreshold slopes of 108 mV/dec. Here, represents the maximum among the top-gate TFTs made on an amorphous SiO substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO channel layer of 4.5 nm and an HfO gate dielectric with a 3 nm SiO interfacial layer between the SnO and HfO. The inserted SiO layer is crucial for decreasing the charged defect scattering in the HfO and HfO/SnO interfaces to increase the mobility. Such high , large I, and low I top-gate SnO devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.
金属氧化物薄膜晶体管（TFT）已被应用于显示面板，但未来的应用还需要进一步提高其迁移率。在本研究中，顶栅共面二元SnO TFT表现出优异的性能，其场效应迁移率（）高达136 cm²/V·s，开态电流/关态电流（Ion/Ioff）为1.5×10⁶，亚阈值斜率低至108 mV/dec。这里，代表在非晶硅氧化物（SiO）衬底上制作的顶栅TFT中的最大值，最高工艺温度≤400°C。与底栅器件不同，顶栅器件是单片集成电路（IC）的标准结构。通过使用4.5 nm的超薄SnO沟道层和具有3 nm SiO界面层的HfO栅极电介质，实现了如此卓越的器件完整性，该界面层位于SnO和HfO之间。插入的SiO层对于减少HfO以及HfO/SnO界面处的带电缺陷散射以提高迁移率至关重要。这种具有共面结构、高迁移率、大开态电流和低关态电流的顶栅SnO器件对于显示器、动态随机存取存储器和单片三维IC来说非常重要。
