Yen Te Jui, Chin Albert, Gritsenko Vladimir
Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
Rzhanov Institute of Semiconductor Physics, Siberian Branch, Russian Academy of Sciences, Novosibirsk 630090, Russia.
Nanomaterials (Basel). 2021 Jan 3;11(1):92. doi: 10.3390/nano11010092.
Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility () and large on-current/off-current (I/I) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high of 4.4 cm/Vs, large I/I of 1.2 × 10, and sharp transistor's turn-on subthreshold slopes () of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO/SnO interface and related were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn-O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO to demote the device performance. The hole , I/I, and values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.
实现用于单片三维（3D）集成电路（IC）和低直流功耗显示器的高性能n型和p型薄膜晶体管（TFT）至关重要。为实现这些目标，与传统的底栅结构相比，顶栅晶体管更受青睐。然而，要实现具有良好空穴场效应迁移率（）和大的开/关电流比（I/I）的高性能顶栅p型TFT具有挑战性。在本报告中，同时实现了共面顶栅纳米片SnO p型TFT，其具有4.4 cm²/V·s的高迁移率、1.2×10⁶的大I/I比以及526 mV/十倍频程的尖锐晶体管开启亚阈值斜率（）。二次离子质谱分析表明，优异的器件完整性与工艺温度密切相关，因为由于Sn-O键能较弱，在高温下Sn和Hf的相互扩散会使HfO₂/SnO₂界面及相关性能退化。工艺过程中的氧含量也至关重要，因为空穴导电的p型SnO₂沟道会被氧化成富氧的n型SnO₂，从而降低器件性能。本研究中获得的空穴迁移率、I/I比和亚阈值斜率值是迄今为止顶栅p型TFT器件报告的最佳数据，因此有助于在IC芯片的后端电介质上开发单片3D IC。
