Chen Ruibo, Liu Hongxia, Song Wenqiang, Du Feibo, Zhang Hao, Zhang Jikai, Liu Zhiwei
Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi'an, 710071, China.
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, China.
Nanoscale Res Lett. 2020 Nov 11;15(1):212. doi: 10.1186/s11671-020-03437-3.
Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.
低压触发可控硅整流器（LVTSCR）有望为低压集成电路提供静电放电（ESD）保护。然而，由于其极低的保持电压，它通常容易受到闩锁效应的影响。本文提出了一种新型的嵌入额外p型MOSFET的LVTSCR，即EP-LVTSCR，并在28纳米CMOS技术中得到验证。所提出的器件具有约6.2 V的较低触发电压和约5.5 V的显著更高的保持电压，在传输线脉冲测试下故障电流仅下降23%。还表明，EP-LVTSCR在3.63 V下测量时具有约1.8 Ω的较低导通电阻以及约1.8 nA的可靠泄漏电流，使其适用于2.5 V/3.3 V CMOS工艺中的ESD保护。此外，通过TCAD模拟探索并展示了所提出器件的触发机制和传导特性。
