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采用原子层沉积制备的未掺杂HfO薄膜的金属-铁电体-金属-绝缘体-半导体栅堆叠结构铁电场效应晶体管中氧化栅电极的影响

Impact of oxide gate electrode for ferroelectric field-effect transistors with metal-ferroelectric-metal-insulator-semiconductor gate stack using undoped HfO thin films prepared by atomic layer deposition.

作者信息

Choi Se-Na, Moon Seung-Eon, Yoon Sung-Min

机构信息

Department of Advanced Materials Engineering for Information and Electronics, Kyung Hee University, Yongin, Gyeonggi-do 17104, Republic of Korea.

Electronics and Telecommunications Research Institute, Daejeon 34129, Republic of Korea.

出版信息

Nanotechnology. 2021 Feb 19;32(8):085709. doi: 10.1088/1361-6528/abc98c.

Abstract

Ferroelectric field-effect transistors (FETs) with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gate stack were fabricated and characterized to elucidate the key process parameters and to optimize the process conditions for guaranteeing nonvolatile memory operations of the device when the undoped HfO was employed as ferroelectric gate insulator. The impacts of top gate (TG) for the MFM part on the memory operations of the MFMIS-FETs were intensively investigated when the TG was chosen as metal Pt or oxide ITO electrode. The ferroelectric memory window of the MFMIS-FETs with ITO/HfO/TiN/SiO/Si gate stack increased to 3.8 V by properly modulating the areal ratio between two MFM and MIS capacitors. The memory margin as high as 10 was obtained during on- and off-program operations with a program pulse duration as short as 1 μs. There was not any marked degradation in the obtained memory margin even after a lapse of retention time of 10 s at 85 °C and repeated program cycles of 10,000. These obtained improvements in memory operations resulted from the fact that the choice of ITO TG could provide effective capping effects and passivate the interfaces.

摘要

制备并表征了具有金属 - 铁电体 - 金属 - 绝缘体 - 半导体(MFMIS)栅堆叠结构的铁电场效应晶体管(FET),以阐明关键工艺参数,并优化工艺条件,从而在使用未掺杂的HfO作为铁电栅绝缘体时确保器件的非易失性存储操作。当顶栅(TG)选为金属Pt或氧化物ITO电极时,深入研究了MFM部分的顶栅对MFMIS - FET存储操作的影响。通过适当调节两个MFM和MIS电容器之间的面积比,具有ITO/HfO/TiN/SiO/Si栅堆叠结构的MFMIS - FET的铁电存储窗口增加到3.8 V。在编程脉冲持续时间短至1 μs的开编程和关编程操作期间,获得了高达10的存储裕度。即使在85°C下保持10 s的保留时间和10,000次重复编程循环后,所获得的存储裕度也没有任何明显的退化。这些在存储操作方面获得的改进源于这样一个事实,即选择ITO TG可以提供有效的封盖效果并钝化界面。

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